The present invention relates to semiconductor devices, and in particular to Lateral Double Diffused MOSFET (LDMOST) semiconductor devices.
In a conventional LDMOST, a well region and a source region are typically created via a double diffusion process or ion-implantation process by which the well region and source region are formed through a common opening window that is self-aligned to a gate. This technique facilitates control of the lateral diffusion of the impurities under the gate so that small channel lengths can be realized without the use of high-resolution photolithography. An example of a conventional n-well LDMOST 10 is illustrated in FIG. 1, and includes a p-well region 12 and an n+ drain region 16 formed in an n− substrate 18. An n+ source region 14 is formed within the p-well region 12. Current flows laterally from the source region 14 to the drain region 16, when an applicable control voltage is applied to the gate to form a channel (inversion layer) at the surface of the p-well region 12.
The p-well region 12 of the LDMOST is separated from the n+ drain region 16 by an extended and lightly doped region known as a drift region 18. The drift region 18 supports high reverse bias voltage applied at the drain region 16 in an off-state. The vertical pn junction formed between the p-well region 12 and n− drift region 18, however, causes avalanche breakdown to occur at the surface of the device. The breakdown voltage (BV) of the device is less than that of the parallel plane pn diode with similar doping concentrations due to electric field crowding near the surface associated with the shallow and cylindrical shaped junction. To increase the BV of an LDMOST the doping concentration in the drift region 18 must be reduced and the length of the region increased. Such modifications, however, result in an increase in the device specific on-resistance, defined as the product of the device on-resistance and its area.
To overcome the limitations on breakdown voltage inherent in the LDMOST design, a Reduced Surface Field (RESURF) concept has been suggested for the LDMOST. For a detailed description of RESURF technology as incorporated in lateral devices, please see J. A. Appels and H. M. J. Vaes, “High Voltage Thin Layer Devices (RESURF Devices)”, IEEE International Electron Device Meeting (IEDM), Dig. Tech Papers, pp 238–241, 1979, which is incorporated herein by reference. The RESURF concept, as applied to LDMOSTs, provides a mechanism by which the avalanche breakdown at the device surface can be avoided. A cross-section of a RESURF LDMOST (R-LDMOST) 20 implemented on a bulk silicon substrate 22 is illustrated in FIG. 2. Electrical isolation between devices is achieved by junction isolation (JI).
The typical R-LDMOST device is fabricated on a thin epitaxial layer of thickness tepi, for example, the n− epitaxial layer 24 illustrated in FIG. 2. The RESURF technique employs the interaction between the depletion regions of two pn junction diodes to reduce the electric field at the surface. The first pn junction is the vertical junction between the p+ well 28 and the n− epitaxial layer 24. The second pn junction is the horizontal junction formed by the p− substrate 22 and the n− epitaxial layer 24. Both of these junctions are reversed biased.
Surface breakdown of R-LDMOST devices is eliminated by vertically enhancing the depletion of the junction between the p+ well 28 and the n-epitaxial layer 24 and the p− substrate 22 and the n− epitaxial layer 24, so that the drift region is fully depleted before the surface electric field reaches its critical breakdown value. Device breakdown then occurs in the bulk at the parallel plane junction formed between p− substrate 22 and n− epitaxial layer 24. The depletion process is accomplished by controlling the amount of charge carriers in the drift region. Optimum breakdown voltage is achieved provided the product of the epitaxial layer 24 doping concentration ND and the epitaxial layer 24 thickness of tepi is in the order of 1×1012 cm−2 to 2×1012 cm−2. This condition, known as the RESURF condition, puts a limit on the upper bound of the doping concentration in the drift region and hence the minimum achievable specific on-resistance.
The Super Junction concept can be applied to LDMOST devices to increase the device breakdown voltage and decrease the resistivity of the drift region in high voltage LDMOSTs. For a more detailed understanding of Super Junction technology, refer to X. B. Chen, P. A. Mawby, K. Board and C. A. T. Salama, “Theory of a Novel Voltage Sustaining Layer for Power Devices”, Microelectronics Journal, vol. 29, pp. 1005–1011, 1998, or to L. Lorenz, G. Deboy, A. Knapp and M. Marz, “COOLMOS™—A New Milestone in High Voltage Power MOS”, Proceedings of the 11th International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 3–10, 1999, both of which are incorporated herein by reference. For a more explicit explanation of the methods by which SJ regions can be manufactured, refer to T. Nitta, T. Minato, M. Yano, A. Uenisi, M. Harada and S. Hine, “Experimental Results and Simulation Analysis of 250V Super Trench Power MOSFET (STM)”, International Symposium on Power Semiconductor Devices and ICs (ISPSD), Proceedings, pp. 77–80, 2000, the contents of which are incorporated herein by reference.
An example of a Super Junction LDMOST (SJ-LDMOST) known in the prior art is shown in FIG. 3. In the SJ-LDMOST device, the low doped drift region of conventional devices is replaced with a region 32 composed of alternatively stacked, heavily doped n-layers 34 and p-layers 35 called the SJ pillars. The SJ pillars provide a mechanism by which charge compensation can be achieved in the drift region. A SJ drift region 32 is shown in FIG. 4(a). For charge compensation to occur, the pillars must have equal integrated doping levels; i.e. the product of the pillar doping concentration and its width must be identical for all pillars. The condition for charge compensation, assuming uniform doping profile in the pillars is given byq.ND.Yn=q.NA.Yp  (1)where q is the electronic charge and ND, NA are the net impurity doping concentration in the n-pillar and p-pillar respectively and Yn, Yp are the respective widths of the pillars.
When a reverse bias is applied to the structure, the resultant electric field depletes the pillars of their charge carriers, moving them in opposite directions towards their respective ohmic contacts as shown in FIG. 4(a). The depletion region edges spread out into neighboring SJs. The edges of the depletion regions must merge before the maximum field at the junctions reach the critical electric field value. Quantitatively this condition can be expressed as                                           q            ·                          N              D                        ·                          Y              n                                            2            ⁢                          ɛ              s                                      =                                            q              ·                              N                A                            ·                              Y                p                                                    2              ⁢                              ɛ                s                                              <                      E            c                                              (        2        )            where Ec is the critical electric field in silicon and εs is the silicon permittivity. Once the depletion regions of adjacent junctions merge the whole drift region becomes depleted of charge carriers. The bound ion charges in the pillars, which are equal in magnitude but opposite in polarity, cancel each other out causing the net charge across the drift region to be effectively zero. If charge compensation is in effect, a uniform electric field distribution over the drift region is obtained as shown in FIG. 4b. 
The SJ structure results in a flat electric field distribution in the drift region 32 which yields the highest possible breakdown voltage for a given drift region length LD and is independent of the doping concentration in the drift region 32. That breakdown voltage is given byBV=EC.LD  (3)Another advantage of the SJ structure is the significant reduction of the specific on-resistance achieved by using high doping concentration in the n-pillars 34. The doping of the n-pillars 34 can be increased by one to two orders of magnitude as compared to conventional structures, thus compensating for the fact that half of the conducting area in the drift region is lost to the p-pillars.
High performance SJ-LDMOSTs require high and tightly matched pillar doping concentrations. If the pillar doping concentrations are not equal, charge imbalances occur in the pillars and result in a reduction in the breakdown voltage of the SJ device. This degradation effect becomes more pronounced at higher doping concentrations.
The design of the SJ device must also account for the charge imbalance caused by substrate-assisted-depletion. The termination of the SJ device with a substrate 36 of finite resistivity results in a severe reduction of the breakdown voltage. In the off-state, the p-pillars 35 are depleted by two neighboring n-pillars 34 (mutual depletion action), however the n-pillars 34 are depleted by their two neighboring p-pillars 35 as well as by the p− substrate 36 (substrate-assisted-depletion). The mutual depletion action and the substrate-assisted-depletion are depicted in FIG. 5. A vertical electric field component exists between the p− substrate 36 and the n-pillar 34. This electric field component is a function of lateral position along the drift region 32 and causes a surplus of one type of charge in the pillars. The substrate assisted depletion is most severe near the drain contact regions and diminishes quickly towards the p-well 38 as is evident by the equipotential contour plots shown in FIG. 6. The reference numerals of FIG. 6 refer to the following regions: 36 denotes the substrate, 62 the source region of the device, 64 the gate region, 65 the oxide region, 66 the drain region and 68 denotes the edge of the depletion region of the device.